Typically, a digital imager array includes a focal plane array of pixel cells, each one of the cells including a photoconversion device such as, e.g., a photogate, photoconductor, or a photodiode. In a complementary metal oxide semiconductor (CMOS) imager a readout circuit is connected to each pixel cell which typically includes a source follower output transistor. The photoconversion device converts photons to electrons which are typically transferred to a floating diffusion region connected to the gate of the source follower output transistor. A charge transfer device (e.g., transistor) can be included for transferring charge from the photoconversion device to the floating diffusion region. In addition, such imager cells typically have a transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transference. The output of the source follower transistor is a voltage output on a column line when a row select transistor for the row containing the pixel is activated.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. Nos. 6,140,630, 6,376,868, 6,310,366, 6,326,652, 6,204,524, and 6,333,205, assigned to Micron Technology, Inc. The disclosures of each of the forgoing patents are herein incorporated by reference in their entirety.
In a digital CMOS imager, when incident light strikes the surface of a photodiode, electron/hole pairs are generated in the p-n junction of the photodiode. The generated electrons are collected in the n-type region of the photodiode. The photo charge moves from the initial charge accumulation region to a charge collection region, typically a floating diffusion region, or it may be transferred to the floating diffusion region via a transfer transistor. The charge at the floating diffusion region is typically converted to a pixel output voltage by a source follower transistor.
The floating diffusion region of a CMOS imager is typically connected to metal runners by a contact photoresist/etch process that results in a metal to silicon Schottky diode contact. Some processes use a phosphorous plug implant just prior to contact metallization to reduce resistance and improve operation of the Schottky diode. This phosphorous implant can have a detrimental effect during processing of pixels, for example, when forming p-channel transistors phosphorous contamination can counter dope the p+ source and drain regions. The p+ source and drain regions and the more heavily doped conventional phosphorous ohmic contacts are typically formed during the same photoresist/etch step as the phosphorous plug. A method is needed to target implantation of dopants to minimize contamination of adjacent source/drain regions or other components of the pixel.